Since a TFT-LCD becomes smaller in size while a resolution of the TFT-LCD increases continuously, a problem that there is no sufficient space for laying out wires in a Fan-out area increasingly emerges. In order to solve the problem that there is no sufficient space for laying out the wires in the Fan-out area, the wires in the Fan-out area are generally laid out in two layers at present.
As illustrated in FIG. 1, gate lines led from two ends of an Integrated Circuit (IC) chip distribute symmetrically, i.e., which are numbered as 1, 3, 5, 7, 9 and 2, 4, 6 . . . , 8, 10, respectively, the gate lines led from each end of the chip are laid out alternatively in two layers of metal. The gate lines 1, 5, 9 . . . are located in a same layer of metal (S/D layer, a source layer), and the gate lines 3, 7, . . . are located in a same layer of metal (a gate Layer); the gate lines 2, 6, 10 . . . are located in a same layer of metal (the gate layer), and the gate lines 4, 8, . . . are located in a same layer of metal (the S/D layer); a gate line a in a valid display area is connected to a gate line 1 in the S/D layer of the Fan-out area, and a gate line b in the valid display area is connected to a gate line 2 in the gate layer of the Fan-out area. As the two layers of metal, i.e., the gate layer of metal and the S/D layer of metal are different in materials and thickness, an impedance of the wires in the gate layer and that in the S/D layer are different from each other, and thus a signal value at the gate line a is different from that at the gate line b in the valid display area, which results in variance in charging effects one of the gate lines in different rows in the valid display area, so that a H-line Mura (horizontal line Mura) occurs, and a the picture in which the H-line Mura occurs presents unevenness color and thus a quality of the picture is deteriorated when the picture is played back.
Today, there is not any one improved solution for eliminating the H-line Mura.